《PrimeTime》(primetime)
电驴资源
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| [PrimeTime].primetime_2004.06sp1.rar | 169.16 MB |
| 169.16 MB | |
电驴资源简介
简介:
软件名称：PrimeTime
版本号： 2004-06
软件语言： 英文
运行环境： linux Redhat 7.2 8.0 9.0/Redhat ES3
软件大小： 169 MB
软件分类： EDA/ASIC/静态时序分析工具
主要内容如下：
图片资料实在是没有。
PrimeTime
PrimeTime reg; is a full-chip, gate-level static timing analysis (STA) tool for 100 million-gate designs. PrimeTime provides a comprehensive solution that combines static timing analysis, accurate RC delay calculation, advanced modeling, and timing sign-off in an easy-to-use product. PrimeTime’s performance enables multiple full-chip timing analysis runs of multimilliongate designs while exhaustively analyzing all critical paths. It is ideal for large, multi-frequency designs that combine synthesized logic, embedded memories, and microprocessor cores.
Key benefits:
1 Industry-leading performance and capacity–64-bit architecture allows full-chip timing analysis of 100-million gate designs; Incremental analysis reduces runtimes for minor design changes and improves productivity; Support for binary parasitics
2 Golden delay calculator–Built-in RC delay calculation uses parasitic information from SPEF, DSPF, and RSPF files; Widely adopted in flows worldwide
3 Advanced modeling–Interface Logic Models (ILMs) for hierarchical static timing analysis and sign-off; Extracted Timing Models (ETM) for cell-based reusable IP and physical synthesis design flows; ASIC vendor sign-off and foundry support
这是业界最流行的静态时序分析工具。大部分的公司都是采用该产品来做ｓｉｇｎｏｆｆ的（流片之前最后的验证）。
软件名称：PrimeTime
版本号： 2004-06
软件语言： 英文
运行环境： linux Redhat 7.2 8.0 9.0/Redhat ES3
软件大小： 169 MB
软件分类： EDA/ASIC/静态时序分析工具
主要内容如下：
图片资料实在是没有。
PrimeTime
PrimeTime reg; is a full-chip, gate-level static timing analysis (STA) tool for 100 million-gate designs. PrimeTime provides a comprehensive solution that combines static timing analysis, accurate RC delay calculation, advanced modeling, and timing sign-off in an easy-to-use product. PrimeTime’s performance enables multiple full-chip timing analysis runs of multimilliongate designs while exhaustively analyzing all critical paths. It is ideal for large, multi-frequency designs that combine synthesized logic, embedded memories, and microprocessor cores.
Key benefits:
1 Industry-leading performance and capacity–64-bit architecture allows full-chip timing analysis of 100-million gate designs; Incremental analysis reduces runtimes for minor design changes and improves productivity; Support for binary parasitics
2 Golden delay calculator–Built-in RC delay calculation uses parasitic information from SPEF, DSPF, and RSPF files; Widely adopted in flows worldwide
3 Advanced modeling–Interface Logic Models (ILMs) for hierarchical static timing analysis and sign-off; Extracted Timing Models (ETM) for cell-based reusable IP and physical synthesis design flows; ASIC vendor sign-off and foundry support
这是业界最流行的静态时序分析工具。大部分的公司都是采用该产品来做ｓｉｇｎｏｆｆ的（流片之前最后的验证）。